1. Field of the Invention
The present invention relates to integrated network devices having Peripheral Component Interconnect (PCI) bridges.
2. Background Art
Peripheral Component Interconnect (PCI) interfaces have been used to provide high-speed connectivity between devices in a multi-device system, such as a processor based system such as a personal computer.
FIG. 1 is a diagram illustrating a conventional implementation of a PCI bus system architecture 100. The system 100 includes a processor 102 coupled to a memory controller 104 via a local bus 106. The processor 102 and the memory controller 104 are coupled to a PCI local bus 106 (labeled PCI Local Bus #0) via a host bridge 108.
The host bridge 108 provides a low latency path through which the processor 102 may directly access PCI devices 110, for example a network interface card 111a providing access to a local area network, a disc drive (SCSI) controller 110b providing access to disk drives 114, an audio card 10c, a motion picture card 111d, or a graphics card 110e configured for driving a monitor 116. The host bridge 108 also provides a high bandwidth path allowing PCI masters on the PCI bus 106 direct access to the system memory 118 via the memory controller 104. A cache memory 120 is independent of the system memory 118 for use by the processor 102.
The term “host bridge” refers to the bridge device 108 that provides access to the system memory 118 for the devices 110 connected to the PCI bus 106. A PCI-to-PCI bridge 122 also may be used to connect a second PCI bus 124 to the PCI bus 106, the second PCI bus 124 configured for connecting other I/O devices 126.
Newer PCI bus protocols are being published, including PCI-X Mode 2, that provide enhanced PCI functionality. These newer PCI bus protocols include the PCI Local Bus Specification, Rev 2.3, the PCI-X Protocol Addendum to the PCI Local Bus Specification, Rev. 2.0a, and the PCI-to-PCI Bridge Architecture Specification, Rev 1.2.
A particular problem encountered during development of new devices involves providing sufficient functionality within the new devices for configuration and testing, thereof, without substantially increasing the cost, complexity, or size of the new device. In particular, there is a desirability to improve the ability of controlling (i.e., modifying) the default settings of internal control registers without increasing device cost or complexity.
One technique for modifying default settings involved bypassing initial default settings of internal control registers having been stored in the device within an internal read-only memory (ROM). In particular, the initial default settings are stored in the ROM internal to the device as part of the device manufacture: if the device is implemented as an ASIC, the initial default settings could be stored in the ROM by mask programming. The device also could include an external ROM interface that would enable connection of an external ROM that would include updated default settings that superseded the initial default settings stored internally; hence, on powerup the device could be reprogrammed by its scanning the updated default settings from the external ROM via the external ROM interface, effectively replacing the initial default settings.
Use of an external ROM interface, however, requires extra pins for the device; further, additional logic is needed to interface with the external ROM and read the updated default settings instead of the initial default settings stored in the internal ROM. Further, the necessity of an external ROM requires reserving valuable space on a circuit board, and provides substantial difficulties when attempting to retrofit an external ROM onto a circuit board manufactured according to surface mount technology.
Problems also have been encountered in attempts to debug a new integrated (i.e., single-chip) device. In particular, previous device designs have implemented “debug modes”, where internal multiplexers and associated logic have been implemented within the new device to output internal state information onto at least selected portions of the PCI bus for analysis. In particular, a user would connect a logic analyzer to the associated pins of the PCI bus in order to capture the signal traces output by the associated pins during debug mode.
Use of a logic analyzer, however, creates difficulties in attempting to connect the logic analyzer to the relevant device pins; further, use of a logic analyzer while the device is in debug mode requires configuring the device to output a given internal state, capturing the signal traces from the PCI bus, and then later retrieving and reviewing the stored signal traces in an attempt to reconstruct the internal state: such a tedious process may be impractical in certain situations, for example when attempting troubleshooting at a customer site.
The Joint Test Action Group (JTAG) published IEEE 1149.x, “IEEE Standard Test Access Port and Boundary-Scan Architecture” (referred to herein as the “JTAG Specification”). The JTAG features normally have been used to facilitate production testing of printed circuit boards. In particular, the JTAG Specification defines test logic that can be included in an integrated circuit to provide standardized approaches for testing interconnections between integrated circuits mounted on a printed circuit board. The JTAG Specification overcomes difficulties in testing printed circuit boards implemented based on surface mount interconnection technology by defining a framework for conveying test data to or from the boundaries of individual components so that they can be tested as if they were freestanding.
Hence, a “boundary scan interface” has boundary-scan register cells connected to pins of a component to form a shift register chain around the border of the design of the component. Hence, the JTAG Specification allows interconnections between components to be tested without the necessity of a complex “bed-of-nails” type testing system. Further, the JTAG Specification allows components on the board to be tested by isolating on-chip system logic from external stimuli from surrounding components while performing an internal self-test of the on-chip system logic; alternatively, a static test of the on-chip system logic can be implemented by supplying test data to the component via the JTAG interface, and examining the test results output via the JTAG interface.